VHDL coding for Digital clock

Digital clock in VHDL

     Here is a program for Digital clock in VHDL.The module has one input 'clk' and 3 outputs.Each output represents time in seconds,minutes and in hours.The module has two processes.One of them generate the necessary clock frequency needed to drive the digital clock.The main clock frequency applied to the module is 100 MHz.But our digital clock has to be driven at only 1 Hz.The first process does the necessary clock division needed for this.
     The second process increment the seconds,minutes and hours etc when the conditions are met.For example at every clock cycle we increment 'seconds'.Whenever seconds reaches the value '60' we increment 'minutes' by 1.Similarly whenever minutes reach '60' we increment 'hours' by 1.Once hours reaches the value '23' we reset the digital clock.The VHDL code for digital clock is given below:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity digi_clk is
port (clk1 : in std_logic;
      seconds : out std_logic_vector(5 downto 0);
      minutes : out std_logic_vector(5 downto 0);
      hours : out std_logic_vector(4 downto 0)
     );
end digi_clk;

architecture Behavioral of digi_clk is
signal sec,min,hour : integer range 0 to 60 :=0;
signal count : integer :=1;
signal clk : std_logic :='0';
begin
seconds <= conv_std_logic_vector(sec,6);
minutes <= conv_std_logic_vector(min,6);
hours <= conv_std_logic_vector(hour,5);

 --clk generation.For 100 MHz clock this generates 1 Hz clock.
process(clk1)
begin
if(clk1'event and clk1='1') then
count <=count+1;
if(count = 50000000) then
clk <= not clk;
count <=1;
end if;
end if;
end process;

process(clk)   --period of clk is 1 second.
begin

if(clk'event and clk='1') then
sec <= sec+ 1;
if(sec = 59) then
sec<=0;
min <= min + 1;
if(min = 59) then
hour <= hour + 1;
min <= 0;
if(hour = 23) then
hour <= 0;
end if;
end if;
end if;
end if;

end process;

end Behavioral;

    This digital clock can be used as a component in your main program.If you want to display the time in LCD panel or use a speaker to tell the time then you need to write the appropriate VHDL code for interfacing with such components in your FPGA board.Such programs may vary depending upon the board and FPGA chip you are using.