Here is the code for 4 : 1 MUX using case statements.The module
contains 4 single bit input lines and one 2 bit select input.The output
is a single bit line.
The code was synthesized using XILINX ISE XST . The RTL schematic of the design is shown below.
Note :- Use RTL Viewer to get a closer look on how your design is implemented in hardware.
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity multiplexer4_1 is
port (
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
sel : in std_logic_vector(1 downto 0);
bitout : out std_logic
);
end multiplexer4_1;
architecture Behavioral of multiplexer4_1 is
begin
process(i0,i1,i2,i3,sel)
begin
case sel is
when "00" => bitout <= i0;
when "01" => bitout <= i1;
when "10" => bitout <= i2;
when others => bitout <= i3;
end case;
end process;
end Behavioral;
The testbench code used for testing the code is given below:use IEEE.STD_LOGIC_1164.ALL;
entity multiplexer4_1 is
port (
i0 : in std_logic;
i1 : in std_logic;
i2 : in std_logic;
i3 : in std_logic;
sel : in std_logic_vector(1 downto 0);
bitout : out std_logic
);
end multiplexer4_1;
architecture Behavioral of multiplexer4_1 is
begin
process(i0,i1,i2,i3,sel)
begin
case sel is
when "00" => bitout <= i0;
when "01" => bitout <= i1;
when "10" => bitout <= i2;
when others => bitout <= i3;
end case;
end process;
end Behavioral;
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
SIGNAL i0,i1,i2,i3,bitout : std_logic:='0';
SIGNAL sel : std_logic_vector(1 downto 0):="00";
BEGIN
UUT : entity work.multiplexer4_1 port map(i0,i1,i2,i3,sel,bitout);
tb : PROCESS
BEGIN
i0<='1';
i1<='0';
i2<='1';
i3<='0';
sel <="00";
wait for 2 ns;
sel <="01";
wait for 2 ns;
sel <="10";
wait for 2 ns;
sel <="11";
wait for 2 ns;
--more input combinations can be given here.
END PROCESS tb;
END;
The simulated testbench waveform is shown below:USE ieee.std_logic_1164.ALL;
ENTITY testbench IS
END testbench;
ARCHITECTURE behavior OF testbench IS
SIGNAL i0,i1,i2,i3,bitout : std_logic:='0';
SIGNAL sel : std_logic_vector(1 downto 0):="00";
BEGIN
UUT : entity work.multiplexer4_1 port map(i0,i1,i2,i3,sel,bitout);
tb : PROCESS
BEGIN
i0<='1';
i1<='0';
i2<='1';
i3<='0';
sel <="00";
wait for 2 ns;
sel <="01";
wait for 2 ns;
sel <="10";
wait for 2 ns;
sel <="11";
wait for 2 ns;
--more input combinations can be given here.
END PROCESS tb;
END;
The code was synthesized using XILINX ISE XST . The RTL schematic of the design is shown below.
Note :- Use RTL Viewer to get a closer look on how your design is implemented in hardware.
Hi Aravind,
ReplyDeleteA really interesting, clear and easily readable Simple 4 : 1 multiplexer using case statements article of interesting and different perspectives. I will clap. So much is so well covered here.
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Anyways great write up, your efforts are much appreciated.
Grazie,
Abhiram
Hi Aravind,
ReplyDeleteSimple 4: 1 multiplexer using case statements being contrived to exist for many projects simply so it can be run will be the first to hit the wall, but those projects where the functions to make existing transactions cheaper in real world applications will find the elusive `real-world demand.
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I read multiple articles and watched many videos about how to use this tool - and was still confused! Your instructions were easy to understand and made the process simple.
Cheers,
Kevin
Hello Arvind,
ReplyDeleteBest thing I have read in a while on this Simple 4 : 1 multiplexer using case statements . There should be a standing ovation button. This is a great piece. AWS Tutorial
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By the way do you have any YouTube videos, would love to watch it. I would like to connect you on LinkedIn, great to have experts like you in my connection (In case, if you don’t have any issues).
Shukran,
Radhey
Hi Aravind,
ReplyDeleteI learnt so much in such little time about Simple 4 : 1 multiplexer using case statements. Even a toddler could become smart reading of your amazing articles.
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Anyways great write up, your efforts are much appreciated.
Merci,
Kevin
Hi Bru,
ReplyDeleteI’ve often thought about this Simple 4 : 1 multiplexer using case statements. Nice to have it laid out so clearly. Great eye opener.
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But nice Article Mate! Great Information! Keep up the good work!
Thanks a heaps,
Radhey