Usage of components and Port mapping methods

Suppose your design is a hierarchical model.This means that you have one top module which contains some sub-modules in it.For instance you can construct a full adder using two half adders.In this case your full adder is the top module and half adder is the sub module.
     As the full adder consists of two sub-modules, they have to be "introduced" first.This is done using a component declaration in which all module types which will be used, are declared. This declaration has to occur before the 'begin' keyword of the architecture statement.
    Now you have to tell the number of half adder's to be used.This is done by instantiating the declared component.Each component instance is given a unique name (label) by the designer, together with the name of the component itself. Component instantiations are done in the definition part of an architecture (after the keyword 'begin').
    Now you have to connect the component ports to the rest of the circuit.A keyword named "port map" is used for this purpose. It has to list the names of the architecture signals that shall be used in the sub-module.
Now let us understand this by an example.VHDL code is written for the following design.

--top module(full adder) entity declaration
entity fulladder is
    port (a : in std_logic;
            b : in std_logic;
           cin : in std_logic;
           sum : out std_logic;
           carry : out std_logic
         );
end fulladder;
--top module architecture declaration.
architecture behavior of fulladder is
--sub-module(half adder) is declared as a component before the keyword "begin".
   component halfadder
    port(
         a : in std_logic;
         b : in std_logic;
         sum : out std_logic;
         carry : out std_logic
        );
    end component;
--All the signals are declared here,which are not a part of the top module.
--These are temporary signals like 'wire' in Verilog.
signal s1,c1,c2 : std_logic:='0';

begin
--instantiate and do port map for the first half adder.
  HA1 : halfadder port map (
          a => a,
          b => b,
          sum => s1,
          carry => c1
        );
--instantiate and do port map for the second half adder.
 HA2 : halfadder port map (
          a => s1,
          b => cin,
         sum => sum,
         carry => c2
        );
carry <= c1 or c2;  --final carry calculation

end;

In the above method of port mapping we can map the input in any order.I mean whether "a=>s1" is given first or "b => c" is given first doesnt change the logic or generate an error.

Now let us see another method of portmapping.In this kind of port mapping replace all the contents between "begin" and "end" in the above program with the following two lines.

HA1 : halfadder port map (a,b,s1,c1);
HA2 : halfadder port map (s1,cin,sum,c2);
carry <= c1 or c2;

The order in which we write the signal names inside the brackets are important here.This method, if carefully
written is a great way to reduce unnecassary length of the code.

Note :- Components are valuable part of design when it comes to hierarchical design.It is important to declare and instantiate them properly for your design to work correctly.