4 bit Synchronous UP counter(with reset) using JK flip-flops

Here is the code for 4 bit Synchronous UP counter.The module uses positive edge triggered JK flip flops for the counter.The counter has also a reset input.The JK flipflop code used is from my previous blog.For simulating this counter code,copy and paste the JK flipflop code available at the above link in a file and store the file in the same directory with other .vhd files.
The top module code is given below:

--libraries to be used are specified here
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

--entity declaration with port definitions
entity syn_count4 is
port ( clk:     in std_logic;
          reset:      in std_logic;
          counter : out std_logic_vector(3 downto 0)
);
end syn_count4;

--architecture of entity
architecture Behavioral of syn_count4 is
--signal declaration.
signal J3,J4,Q1,Q2,Q3,Q4,Qbar1,Qbar2,Qbar3,Qbar4 : std_logic :='0';

begin
J3 <= Q1 and Q2;
J4<= J3 and Q3;
--entity instantiations
FF1 : entity work.JK_Flipflop port map (clk,'1','1',Q1,Qbar1,reset);
FF2 : entity work.JK_Flipflop port map (clk,Q1,Q1,Q2,Qbar2,reset);
FF3 : entity work.JK_Flipflop port map (clk,J3,J3,Q3,Qbar3,reset);
FF4 : entity work.JK_Flipflop port map (clk,J4,J4,Q4,Qbar4,reset);
counter <= Q4 & Q3 & Q2 & Q1;

end Behavioral;

The test bench program used for testing the design is given below:

--libraries to be used are specified here
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity testbench is
end testbench;

architecture behavior of testbench is
--Signal declarations
signal clk,reset : std_logic := '0';
signal counter : std_logic_vector(3 downto 0):="0000";
-- Clock period definitions
constant clk_period : time := 1 ns;

begin
-- Instantiate the Unit Under Test (UUT)
UUT : entity work.syn_count4 port map (clk,reset,counter);

-- Clock process definitions
clk_process :process
begin
        clk <= '0';
        wait for clk_period/2;
        clk <= '1';
        wait for clk_period/2;
end process;

-- Stimulus process
stim_proc: process
begin        
wait for clk_period*20;
reset <='1';
wait for clk_period*2;
reset <='0';
end process;

end;

   The simulated waveform is shown below.Note that when reset is '1' the counter value is reset to "0000" and remains zero till the reset input equals to '0' again.

The code was synthesized using XILINX ISE XST . The RTL schematic of the design is shown below:

Note :- Use RTL Viewer to get a closer look on how your design is implemented in hardware.