ABSTRACT
Security
is prime concern in our day-to-day life. Every one wants to be as much
as secure as to be possible. An access control systems forms a vital
link in a security chain. The micro controller based digital lock
presented here is an access control system that allows only authorized
persons to access a restricted area. This system is best suitable for
corporate offices, ATMs and home security.
The system comprises
a small electronic unit with a numeric keypad, which is fixed out side
the entry door to control a solenoid-operated lock with the help of a
stepper motor. When an authorized person enters predetermined user ID
and password via the keypad, the stepper motor is operated for a limited
time to unlatch the solenoid-operated lock so the door can be open. At
the end of preset delay, the stepper motor is operated in reverse
direction and the door gets locked again.
When the code has
been incorrectly entered three times in a row, the code lock will switch
to block mode. This function thwarts any attempt by ‘hackers’ to
quickly try a large number of codes in a sequence. If the user forgets
his password, the code lock can be accessed by a unique 10 digit
administrator password. The secret code can be changed any time after
entering the current code (Master code).
A buzzer is provided
for audio acknowledgment of the key impression. Whenever a key is
pressed on the numeric key pad, the system acknowledges the impression
by a short beep sound. This buzzer is driven by an NPN transistor.
This
project uses regulated 5V, 500mA power supply. 7805 three terminal
voltage regulator is used for voltage regulation. Bridge type full wave
rectifier is used to rectify the ac out put of secondary of 230/12V step
down transformer.
INTRODUCTION
An embedded system is a combination of software and hardware to perform a dedicated task.
Some of the main devices used in embedded products are Microprocessors and Microcontrollers.
Microprocessors
are commonly referred to as general purpose processors as they simply
accept the inputs, process it and give the output.
In contrast,
a microcontroller not only accepts the data as inputs but also
manipulates it, interfaces the data with various devices, controls the
data and thus finally gives the result.
The Project Embedded
Password based Electrical Appliances control system using 89C51
Microcontroller is an excellent project that provides security in every
way. This project is very useful in places where security is must.
BLOCK DIAGRAM
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Transistor Driver
Circuit
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BLOCK DESCRIPTION
POWER SUPPLY:
The
input to the circuit is applied from the regulated power supply. The
a.c. input i.e., 230V from the mains supply is step down by the
transformer to 12V and is fed to a rectifier. The output obtained from
the rectifier is a pulsating d.c voltage. So in order to get a pure d.c
voltage, the output voltage from the rectifier is fed to a filter to
remove any a.c components present even after rectification. Now, this
voltage is given to a voltage regulator to obtain a pure constant dc
voltage.
Fig: Power supply
Transformer:
Usually,
DC voltages are required to operate various electronic equipment and
these voltages are 5V, 9V or 12V. But these voltages cannot be obtained
directly. Thus the a.c input available at the mains supply i.e., 230V is
to be brought down to the required voltage level. This is done by a
transformer. Thus, a step down transformer is employed to decrease the
voltage to a required level.
Rectifier:
The
output from the transformer is fed to the rectifier. It converts A.C.
into pulsating D.C. The rectifier may be a half wave or a full wave
rectifier. In this project, a bridge rectifier is used because of its
merits like good stability and full wave rectification.
Filter:
Capacitive
filter is used in this project. It removes the ripples from the output
of rectifier and smoothens the D.C. Output received from this filter is
constant until the mains voltage and load is maintained constant.
However, if either of the two is varied, D.C. voltage received at this
point changes. Therefore a regulator is applied at the output stage.
Voltage regulator:
As
the name itself implies, it regulates the input applied to it. A
voltage regulator is an electrical regulator designed to automatically
maintain a constant voltage level. In this project, power supply of 5V
and 12V are required. In order to obtain these voltage levels, 7805 and
7812 voltage regulators are to be used. The first number 78 represents
positive supply and the numbers 05, 12 represent the required output
voltage levels.
MICROCONTROLLERS:
Microprocessors and microcontrollers are widely used in embedded systems products.
Microcontroller is a programmable device.
A microcontroller has a CPU in addition to a fixed amount of RAM, ROM,
I/O ports and a timer embedded all on a single chip. The fixed amount of
on-chip ROM, RAM and number of I/O ports in microcontrollers makes them
ideal for many applications in which cost and space are critical.
The
Intel 8051 is a Harvard architecture, single chip microcontroller (µC)
which was developed by Intel in 1980 for use in embedded systems. It was
popular in the 1980s and early 1990s, but today it has largely been
superseded by a vast range of enhanced devices with 8051-compatible
processor cores that are manufactured by more than 20 independent
manufacturers including Atmel, Infineon Technologies and Maxim
Integrated Products.
8051 is an 8-bit processor, meaning that
the CPU can work on only 8 bits of data at a time. Data larger than 8
bits has to be broken into 8-bit pieces to be processed by the CPU. 8051
is available in different memory types such as UV-EPROM, Flash and
NV-RAM.
The present project is implemented on Keil Uvision. In
order to program the device, Proload tool has been used to burn the
program onto the microcontroller.
The features, pin description of the microcontroller and the software tools used are discussed in the following sections.
FEATURES OF AT89C51:
Ø 4K Bytes of Re-programmable Flash Memory.
Ø RAM is 128 bytes.
Ø 2.7V to 6V Operating Range.
Ø Fully Static Operation: 0 Hz to 24 MHz.
Ø Two-level Program Memory Lock.
Ø 128 x 8-bit Internal RAM.
Ø 32 Programmable I/O Lines.
Ø Two 16-bit Timer/Counters.
Ø Six Interrupt Sources.
Ø Programmable Serial UART Channel.
Ø Low-power Idle and Power-down Modes.
Description:
The
AT89C51 is a low-voltage, high-performance CMOS 8-bit microcomputer
with 4K bytes of Flash programmable memory. The device is manufactured
using Atmel’s high-density nonvolatile memory technology and is
compatible with the industry-standard MCS-51 instruction set. By
combining a versatile 8-bit CPU with Flash on a monolithic chip, the
Atmel AT89C51 is a powerful microcomputer, which provides a highly
flexible and cost-effective solution to many embedded control
applications.
In addition, the AT89C51 is designed with static
logic for operation down to zero frequency and supports two software
selectable power saving modes. The Idle Mode stops the CPU while
allowing the RAM, timer/counters, serial port and interrupt system to
continue functioning. The power-down mode saves the RAM contents but
freezes the oscillator disabling all other chip functions until the next
hardware reset.
Fig: Pin diagram
Fig: Block diagram
PIN DESCRIPTION:
Vcc
Pin 40 provides supply voltage to the chip. The voltage source is +5V.
GND
Pin 20 is the ground.
XTAL1 and XTAL2
XTAL1
and XTAL2 are the input and output, respectively, of an inverting
amplifier that can be configured for use as an on-chip oscillator, as
shown in Figure 11. Either a quartz crystal or ceramic resonator may be
used. To drive the device from an external clock source, XTAL2 should be
left unconnected while XTAL1 is driven, as shown in the below figure.
There are no requirements on the duty cycle of the external clock
signal, since the input to the internal clocking circuitry is through a
divide-by-two flip-flop, but minimum and maximum voltage high and low
time specifications must be observed.
Fig: Oscillator Connections
C1, C2 = 30 pF ± 10 pF for Crystals
= 40 pF ± 10 pF for Ceramic Resonators
Fig: External Clock Drive Configuration
RESET
Pin9
is the reset pin. It is an input and is active high. Upon applying a
high pulse to this pin, the microcontroller will reset and terminate all
the activities. This is often referred to as a power-on reset.
EA (External access)
Pin
31 is EA. It is an active low signal. It is an input pin and must be
connected to either Vcc or GND but it cannot be left unconnected.
The
8051 family members all come with on-chip ROM to store programs. In
such cases, the EA pin is connected to Vcc. If the code is stored on an
external ROM, the EA pin must be connected to GND to indicate that the
code is stored externally.
PSEN (Program store enable)
This is an output pin.
ALE (Address latch enable)
This is an output pin and is active high.
Ports 0, 1, 2 and 3
The
four ports P0, P1, P2 and P3 each use 8 pins, making them 8-bit ports.
All the ports upon RESET are configured as input, since P0-P3 have value
FFH on them.
Port 0(P0)
Port 0 is also
designated as AD0-AD7, allowing it to be used for both address and data.
ALE indicates if P0 has address or data. When ALE=0, it provides data
D0-D7, but when ALE=1, it has address A0-A7. Therefore, ALE is used for
demultiplexing address and data with the help of an internal latch.
When
there is no external memory connection, the pins of P0 must be
connected to a 10K-ohm pull-up resistor. This is due to the fact that P0
is an open drain. With external pull-up resistors connected to P0, it
can be used as a simple I/O, just like P1 and P2. But the ports P1, P2
and P3 do not need any pull-up resistors since they already have pull-up
resistors internally. Upon reset, ports P1, P2 and P3 are configured as
input ports.
Port 1 and Port 2
With no external
memory connection, both P1 and P2 are used as simple I/O. With external
memory connections, port 2 must be used along with P0 to provide the
16-bit address for the external memory. Port 2 is designated as A8-A15
indicating its dual function. While P0 provides the lower 8 bits via
A0-A7, it is the job of P2 to provide bits A8-A15 of the address.
Port 3
Port
3 occupies a total of 8 pins, pins 10 through 17. It can be used as
input or output. P3 does not need any pull-up resistors, the same as
port 1 and port 2. Port 3 has an additional function of providing some
extremely important signals such as interrupts.
Table: Port 3 Alternate Functions
Machine cycle for the 8051
The
CPU takes a certain number of clock cycles to execute an instruction.
In the 8051 family, these clock cycles are referred to as machine
cycles. The length of the machine cycle depends on the frequency of the
crystal oscillator. The crystal oscillator, along with on-chip
circuitry, provides the clock source for the 8051 CPU.
The
frequency can vary from 4 MHz to 30 MHz, depending upon the chip rating
and manufacturer. But the exact frequency of 11.0592 MHz crystal
oscillator is used to make the 8051 based system compatible with the
serial port of the IBM PC.
In the original version of 8051, one
machine cycle lasts 12 oscillator periods. Therefore, to calculate the
machine cycle for the 8051, the calculation is made as 1/12 of the
crystal frequency and its inverse is taken.
The assembly
language program is written and this program has to be dumped into the
microcontroller for the hardware kit to function according to the
software. The program dumped in the microcontroller is stored in the
Flash memory in the microcontroller. Before that, this Flash memory has
to be programmed and is discussed in the next section.
PROGRAMMING THE FLASH:
The
AT89C51 is normally shipped with the on-chip Flash memory array in the
erased state (that is, contents = FFH) and ready to be programmed. The
programming interface accepts either a high-voltage (12-volt) or a
low-voltage (VCC) program enable signal. The low-voltage programming
mode provides a convenient way to program the AT89C51 inside the user’s
system, while the high-voltage programming mode is compatible with
conventional third party Flash or EPROM programmers. The AT89C51 is
shipped with either the high-voltage or low-voltage programming mode
enabled. The respective top-side marking and device signature codes are
listed in the following table.
The AT89C51 code memory array is programmed byte-byte in either programming mode.
To program any nonblank byte in the on-chip Flash Memory, the entire memory must be erased using the Chip Erase Mode.
Programming Algorithm:
Before
programming the AT89C51, the address, data and control signals should
be set up according to the Flash programming mode table. To program the
AT89C51, the following steps should be considered:
1. Input the desired memory location on the address lines.
2. Input the appropriate data byte on the data lines.
3. Activate the correct combination of control signals.
4. Raise EA/VPP to 12V for the high-voltage programming mode.
5.
Pulse ALE/PROG once to program a byte in the Flash array or the lock
bits. The byte-write cycle is self-timed and typically takes no more
than 1.5 ms.
Repeat steps 1 through 5, changing the address and data for the entire array or until the end of the object file is reached.
Data Polling:
The
AT89C51 features Data Polling to indicate the end of a write cycle.
During a write cycle, an attempted read of the last byte written will
result in the complement of the written datum on PO.7. Once the write
cycle has been completed, true data are valid on all outputs, and the
next cycle may begin. Data Polling may begin any time after a write
cycle has been initiated.
Ready/Busy:
The progress of
byte programming can also be monitored by the RDY/BSY output signal.
P3.4 is pulled low after ALE goes high during programming to indicate
BUSY. P3.4 is pulled high again when programming is done to indicate
READY.
Chip Erase:
The entire Flash array is erased
electrically by using the proper combination of control signals and by
holding ALE/PROG low for 10 ms. The code array is written with all “1”s.
The chip erase operation must be executed before the code memory can be
re programmed.
Reading the Signature Bytes:
The
signature bytes are read by the same procedure as a normal verification
of locations 030H, 031H, and 032H, except that P3.6 and P3.7 must be
pulled to a logic low. The values returned are as follows.
(030H) = 1EH indicates manufactured by Atmel
(031H) = 51H indicates 89C51
(032H) = FFH indicates 12V programming
(032H) = 05H indicates 5V programming
Programming Interface:
Every
code byte in the Flash array can be written and the entire array can be
erased by using the appropriate combination of control signals. The
write operation cycle is self timed and once initiated, will
automatically time itself to completion. All major programming vendors
offer worldwide support for the Atmel microcontroller series.
Fig: Flash Programming Modes
Fig: Programming the Flash
Fig: Verifying the Flash
EEPROM:
In
the design of all microprocessors-based systems, semiconductor memories
are used as primary storage for code and data. Semiconductor memories
are connected directly to the CPU and they are the memory that the CPU
first asks for information (code and data). For this reason,
semiconductor memories are sometimes referred to as primary memory.
Important Terminology common to all Semiconductor Memories:
Memory capacity:
The
number of bits that a semiconductor memory chip can store is called
chip capacity. It can be in units of Kilobits, Megabits and so on. This
must be distinguished from the storage capacity of computer system.
While the memory capacity of a memory IC chip is always given in bits,
the memory capacity of a computer system is given in bytes.
Memory organization:
Memory
chips are organized into a number of locations within the IC. Each
location can hold 1 bit, 4 bits, 8 bits or even 16 bits, depending on
how it is designed internally. The number of bits that each location
within the memory chip can hold is always equal to the number of data
pins on the chip. i.e., the total number of bits that a memory chip can
store is equal to the number of locations times the number of data bits
per location.
Speed:
One of the most important
characteristics of a memory chip is the speed at which its data can be
accessed. The speed of the memory chip is commonly referred to as its
access time. The access time of memory chip varies from a few
nanoseconds to hundreds of nanoseconds, depending on the IC technology
used in the design and fabrication process.
The different types of memories are RAM, ROM, EPROM and EEPROM.
RAM and ROM are inbuilt in the microprocessor.
This
project requires the data such as the user identification number and
password to be stored permanently. Thus this data has to be stored in
such a location where it cannot be erased when power fails and also the
data should be allowed to make changes in it without the system
interface i.e., there should be a provision in such a way that the data
should be accessed (or modified) while it is in system board but not
external erasure and programming. The flash memory inbuilt in the
microcontroller can erase the entire contents in less than a second and
the erasure method is electrical. But the major drawback of Flash memory
is that when flash memory’s contents are erased, the entire device will
be erased but not a desired section or byte.
For this purpose, we prefer EEPROM in our project.
EEPROM (Electrically Erasable Programmable Read only memory)
EEPROM
has several advantages over other memory devices, such as the fact that
its method of erasure is electrical and therefore instant. In addition,
in EEPROM one can select which byte to be erased, in contrast to flash ,
in which the entire contents of ROM are erased. The main advantage of
EEPROM is that one can program and erase its contents while it is in
system board. It does not require physical removal of the memory chip
from its socket. In general, the cost per bit for EEPROM is much higher
when compared to other devices.
The EEPROM used in this project is 24C04 type.
Features of 24C04 EEPROM:
- 1 million erase/write cycles with 40 years data retention.
- Single supply voltage:
3v to 5.5v for st24x04 versions.
2.5v to 5.5v for st25x04 versions.
- Hardware write control versions:
st24w04 and st25w04.
- Programmable write protection.
- Two wire serial interface, fully i2c bus compatible.
- Byte and multibyte write (up to 4 bytes).
- Page write (up to 8 bytes).
- Byte, random and sequential read modes
- Self timed programming cycle
- Automatic address incrementing
- Enhanced ESD/Latch up performances
DIP Pin Connections SO Pin Connection
Fig: Signal Names
Fig: Logic Diagram
DESCRIPTION
The
24C04 is a 4 Kbit electrically erasable programmable memory (EEPROM),
organized as 2 blocks of 256 x8 bits. They are manufactured in ST
Microelectronics’ Hi-Endurance Advanced CMOS technology which guarantees
an endurance of one million erase/write cycles with a data retention of
40 years. Both Plastic Dual-in-Line and Plastic Small Outline packages
are available. The memories are compatible with the I2C standard, two
wire serial interface which uses a bi-directional data bus and serial
clock. The memories carry a built-in 4 bit, unique device identification
code (1010) corresponding to the I2C bus definition. This is used
together with 2 chip enable inputs (E2, E1) so that up to 4 x 4K devices
may be attached to the I2C bus and selected individually. The memories
behave as a slave device in the I2C protocol with all memory operations
synchronized by the serial clock. Read and write operations are
initiated by a START condition generated by the bus master. The START
condition is followed by a stream of 7 bits (identification code 1010),
plus one read/write bit and terminated by an acknowledge bit.
Table: Device Select Mode
Table: Operating Modes
When
writing data to the memory it responds to the 8 bits received by
asserting an acknowledge bit during the 9th bit time. When data is read
by the bus master, it acknowledges the receipt of the data bytes in the
same way. Data transfers are terminated with a STOP condition.
Power On Reset: VCC lock out write protect.
In
order to prevent data corruption and inadvertent write operations
during power up, a Power On Reset (POR) circuit is implemented. Until
the VCC voltage has reached the POR threshold value, the internal reset
is active, all operations are disabled and the device will not respond
to any command. In the same way, when VCC drops down from the operating
voltage to below the POR threshold value, all operations are disabled
and the device will not respond to any command. A stable VCC must be
applied before applying any logic signal.
SIGNAL DESCRIPTIONS
Serial Clock (SCL).
The
SCL input pin is used to synchronize all data in and out of the memory.
A resistor can be connected from the SCL line to VCC to act as a pull
up.
Serial Data (SDA).
The SDA pin is
bi-directional and is used to transfer data in or out of the memory. It
is an open drain output that may be wire-OR’ed with other open drain or
open collector signals on the bus. A resistor must be connected from the
SDA bus line to VCC to act as pull up.
Chip Enable (E1 - E2).
These
chip enable inputs are used to set the 2 least significant bits (b2,
b3) of the 7 bit device select code. These inputs may be driven
dynamically or tied to VCC or VSS to establish the device select code.
Protect Enable (PRE).
The
PRE input pin, in addition to the status of the Block Address Pointer
bit (b2, location 1FFh as in below figure), sets the PRE write
protection active.
Fig: Memory Protection
Mode (MODE).
The
MODE input is available on pin 7 and may be driven dynamically. It must
be at VIL or VIH for the Byte Write mode, VIH for Multibyte Write mode
or VIL for Page Write mode. When unconnected, the MODE input is
internally read as VIH (Multibyte Write mode).
Write Control (WC).
An
hardware Write Control feature (WC) is offered only for ST24W04 and
ST25W04 versions on pin 7. This feature is useful to protect the
contents of the memory from any erroneous erase/write cycle. The Write
Control signal is used to enable (WC = VIH) or disable (WC =VIL) the
internal write protection. When unconnected, the WC input is internally
read as VIL and the memory area is not write protected.
DEVICE OPERATION
I2C Bus Background
The
ST24/25x04 supports the I2C protocol. This protocol defines any device
that sends data onto the bus as a transmitter and any device that reads
the data as a receiver. The device that controls the data transfer is
known as the master and the other as the slave. The master will always
initiate a data transfer and will provide the serial clock for
synchronization.
The ST24/25x04 is always slave devices in all communications.
Fig: I2C Protocol
Start Condition.
START
is identified by a high to low transition of the SDA line while the
clock SCL is stable in the high state. A START condition must precede
any command for data transfer. Except during a programming cycle, the
ST24/25x04 continuously monitor the SDA and SCL signals for a START
condition and will not respond unless one is given.
Stop Condition.
STOP
is identified by a low to high transition of the SDA line while the
clock SCL is stable in the high state. A STOP condition terminates
communication between the ST24/25x04 and the bus master. A STOP
condition at the end of a Read command, after and only after a No
Acknowledge, forces the standby state. A STOP condition at the end of a
Write command triggers the internal EEPROM write cycle.
Acknowledge Bit (ACK).
An
acknowledge signal is used to indicate a successful data transfer. The
bus transmitter, either master or slave, will release the SDA bus after
sending 8 bits of data. During the 9th clock pulse period the receiver
pulls the SDA bus low to acknowledge the receipt of the 8 bits of data.
Data Input.
During
data input the ST24/25x04 sample the SDA bus signal on the rising edge
of the clock SCL. Note that for correct device operation the SDA signal
must be stable during the clock low to high transition and the data must
change ONLY when the SCL line is low.
Memory Addressing.
To
start communication between the bus master and the slave ST24/25x04,
the master must initiate a START condition. Following this, the master
sends onto the SDA bus line 8 bits (MSB first) corresponding to the
device select code (7 bits) and a READ or WRITE bit. The 4 most
significant bits of the device select code are the device type
identifier, corresponding to the I2C bus definition. For these memories
the 4 bits are fixed as 1010b. The following 2 bits identify the
specific memory on the bus. They are matched to the chip enable signals
E2, E1. Thus up to 4 x 4K memories can be connected on the same bus
giving a memory capacity total of 16 Kilobits. After a START condition
any memory on the bus will identify the device code and compare the
following 2 bits to its chip enable inputs E2, E1. The 7th bit sent is
the block number (one block = 256 bytes). The 8th bit sent is the read
or write bit (RW), this bit is set to ’1’ for read and ’0’ for write
operations. If a match is found, the corresponding memory will
acknowledge the identification on the SDA bus during the 9th bit time.
Fig: AC Waveforms
Write Operations
The
Multibyte Write mode (only available on the ST24/25C04 versions) is
selected when the MODE pin is at VIH and the Page Write mode when MODE
pin is at VIL. The MODE pin may be driven dynamically with CMOS input
levels. Following a START condition the master sends a device select
code with the RW bit reset to ’0’. The memory acknowledges this and
waits for a byte address. The byte address of 8 bits provides access to
one block of 256 bytes of the memory. After receipt of the byte address
the device again responds with an acknowledge. For the ST24/25W04
versions, any write command with WC = 1 will not modify the memory
content.
Byte Write.
In the Byte Write mode the
master sends one data byte, which is acknowledged by the memory. The
master then terminates the transfer by generating a STOP condition. The
Write mode is independent of the state of the MODE pin which could be
left floating if only this mode was to be used. However it is not a
recommended operating mode, as this pin has to be connected to either
VIH or VIL, to minimize the stand-by current.
Multibyte Write.
For
the Multibyte Write mode, the MODE pin must be at VIH. The Multibyte
Write mode can be started from any address in the memory. The master
sends from one up to 4 bytes of data, which are each acknowledged by the
memory. The transfer is terminated by the master generating a STOP
condition. The duration of the write cycle is Tw = 10ms maximum except
when bytes are accessed on 2 rows (that is have different values for the
6 most significant address bits A7-A2), the programming time is then
doubled to a maximum of 20ms. Writing more than 4 bytes in the Multibyte
Write mode may modify data bytes in an adjacent row (one row is 8 bytes
long). However, the Multibyte Write can properly write up to 8
consecutive bytes as soon as the first address of these 8 bytes is the
first address of the row, the 7 following bytes being written in the 7
following bytes of this same row.
Page Write.
For
the Page Write mode, the MODE pin must be at VIL. The Page Write mode
allows up to 8 bytes to be written in a single write cycle, provided
that they are all located in the same ’row’ in the memory: that is the 5
most significant memory address bits (A7-A3) are the same inside one
block. The master sends from one up to 8 bytes of data, which are each
acknowledged by the memory. After each byte is transferred, the internal
byte address counter (3 least significant bits only) is incremented.
The transfer is terminated by the master generating a STOP condition.
Care must be taken to avoid address counter ’roll-over’ which could
result in data being overwritten. Note that, for any write mode, the
generation by the master of the STOP condition starts the internal
memory program cycle. All inputs are disabled until the completion of
this cycle and the memory will not respond to any request.
Minimizing System Delays by Polling on ACK.
During
the internal write cycle, the memory disconnects itself from the bus in
order to copy the data from the internal latches to the memory cells.
The maximum value of the write time (Tw) is given from the AC
Characteristics, since the typical time is shorter, the time seen by the
system may be reduced by an ACK polling sequence issued by the master.
Fig: Write Cycle Polling using ACK
Data
in the upper block of 256 bytes of the memory may be write protected.
The memory is write protected between a boundary address and the top of
memory (address 1FFh) when the PRE input pin is taken high and when the
Protect Flag (bit b2 in location 1FFh) is set to ’0’. The boundary
address is user defined by writing it in the Block Address Pointer. The
Block Address Pointer is an 8 bit EEPROM register located at the address
1FFh. It is composed by 5 MSBs Address Pointer, which defines the
bottom boundary address and 3 LSBs which must be programmed at ’0’. This
Address Pointer can therefore address a boundary in steps of 8 bytes.
The sequence to use the Write Protected feature is:
– write the data to be protected into the top of the memory, up to, but not including, location 1FFh;
–
set the protection by writing the correct bottom boundary address in
the Address Pointer (5 MSBs of location 1FFh) with bit b2 (Protect flag)
set to ’0’. Note that for a correct functionality of the memory, all
the 3 LSBs of the Block Address Pointer must also be programmed at ’0’.
The area will now be protected when the PRE input pin is taken High.
While the PRE input pin is read at ’0’ by the memory, the location 1FFh
can be used as a normal EEPROM byte.
Fig: Write Modes Sequence
Read Operations
Read operations are independent of the state of the MODE pin. On delivery, the memory content is set at all "1’s" (or FFh).
Current Address Read.
The
memory has an internal byte address counter. Each time a byte is read,
this counter is incremented. For the Current Address Read mode,
following a START condition, the master sends a memory address with the
RW bit set to ’1’. The memory acknowledges this and outputs the byte
addressed by the internal byte address counter. This counter is then
incremented. The master does NOT acknowledge the byte output, but
terminates the transfer with a STOP condition.
Random Address Read.
A
dummy write is performed to load the address into the address counter.
This is followed by another START condition from the master and the byte
address is repeated with the RW bit set to ’1’. The memory acknowledges
this and outputs the byte addressed. The master has to NOT acknowledge
the byte output, but terminates the transfer with a STOP condition.
Sequential Read.
This
mode can be initiated with either a Current Address Read or a Random
Address Read. However, in this case the master DOES acknowledge the data
byte output and the memory continues to output the next byte in
sequence. To terminate the stream of bytes, the master must NOT
acknowledge the last byte output, but MUST generate a STOP condition.
The output data is from consecutive byte addresses, with the internal
byte address counter automatically incremented after each byte output.
After a count of the last memory address, the address counter will
’roll- over’ and the memory will continue to output data.
Acknowledge in Read Mode.
In
all read modes the ST24/25x04 wait for an acknowledge during the 9th
bit time. If the master does not pull the SDA line low during this time,
the ST24/25x04 terminate the data transfer and switches to a standby
state.
Fig: Read Modes Sequence
KEYPAD:
Keypads
and LCDs are the most widely used input/output devices of the 8051 and a
basic understanding of them is essential. The keypads are mainly three
types:
- 4*3 keypad
- 4*4 keypad
- 4*8 keypad.
The keypad used in this project is 4*3 keypad.
Calculator keypad Telephone keypad
INTERFACING THE KEYPAD TO 8051
At
the lowest level, keyboards are organized in a matrix of rows and
columns. The CPU accesses both rows and columns through ports.
Therefore, with two 8-bit ports, an 8*8 matrix of keys can be connected
to a microprocessor. When a key is pressed, a row and a column make a
contact, otherwise there is no connection between rows and columns. A
single microcontroller (consisting of a microprocessor, RAM, EPROM and
several ports all on a single chip) takes care of hardware and software
interfacing of the keypad. In such systems, it is the function of
programs stored in EPROM of the microcontroller to scan the keys
continuously, identify which one has been activated and present it to
the motherboard.
Fig: 4*3 Matrix Keypad Connections to Ports
Scanning and identifying the key:
The
rows are connected to an output port and the columns are connected to
an input port. If no key has been pressed, reading the input port will
yield 1s for all columns since they are all connected to high (Vcc). If
all the rows are grounded and a key is pressed, one of the columns will
have 0 since the key pressed provides the path to ground. It is the
function of the microcontroller to scan the keypad continuously to
detect and identify the key pressed.
Grounding rows and reading the columns:
To
detect a pressed key, the microcontroller grounds all rows by providing
0 (zero) to the output latch, then it reads the columns. If the data
read from the columns is D2-D0 =111, no key has been pressed and the
process continues until a key press is detected. However, if one of the
column bits has a zero, this means that a key press has occurred i.e.,
for example, if D2-D0=110, this means that a key in the D0 column has
been pressed. After a key press is detected, the microcontroller will go
through a process of identifying the key. Starting with the top row,
the microcontroller grounds it by providing a low to row D0 only and
then it reads the columns. If the data read is all 1s, no key in that
row is activated and the process is moved to the next row. It grounds
the next row, reads the columns and checks for any zero. This process
continues until the row is identified. After identification of the row
in which the key has been pressed, the next task is to find out which
column the pressed key belongs to. Now this will be easy since the
microcontroller knows at any time which row and column are being
accessed.
TRANSISTOR DRIVER CIRCUIT:
Digital
systems and microcontroller pins lack sufficient current to drive the
circuits like buzzer circuits and relay circuits. While these circuits
need around 10milli amps to be energized, the microcontroller’s pin can
provide a maximum of 1-2milli amps current. For this reason, a driver
such as a power transistor is placed in between the microcontroller and
the buzzer.
The operation of this circuit is as follows:
The
input to the base of the transistor is applied from the microcontroller
port pin P1.0. The transistor will be switched on when the base to
emitter voltage is greater than 0.7V (cut-in voltage). Thus when the
voltage applied to the pin P1.0 is high i.e., P1.0=1 (>0.7V), the
transistor will be switched on and thus the buzzer will be activated and
produces a loud noise.
When the voltage at the pin P1.0 is low
i.e., P1.0=0 (<0.7V) the transistor will be in off state and the
buzzer will be off. Thus the transistor acts like a current driver to
operate the buzzer accordingly.
BUZZER INTERFACING WITH THE MICROCONTROLLER:
ULN2003 CURRENT DRIVER:
Fig: DIP 16 Package The
ULN2003 current driver is a high voltage, high current Darlington
arrays each containing seven open collector Darlington pairs with common
emitters. Each channel is rated at 500mA and can withstand peak
currents of 600mA. Suppression diodes are included for inductive load
driving and the inputs are pinned opposite the outputs to simplify board
layout.
These versatile devices are useful for driving a wide
range of loads including solenoids, relays DC motors, LED displays
filament lamps, thermal print heads and high power buffers. This chip is
supplied in 16 pin plastic DIP packages with a copper lead frame to
reduce thermal resistance.
Fig: Pin Connection
This ULN2003 driver can drive seven relays at a time. The pins 8 and 9 provide ground and Vcc respectively.
The working of ULN driver is as follows:
It
can accept seven inputs at a time and produces seven corresponding
outputs. If the input to any one of the seven input pins is high, then
the value at its corresponding output pin will be low, for example if
the input at pin 6 is high, then the value at the corresponding output
i.e., output at pin 11 will be low. Similarly if the input at a
particular pin is low, then the corresponding output will be high.
STEPPER MOTOR:
Fig: Stepper motor
A
stepper motor is a widely used device that translates electrical pulses
into mechanical movement. The stepper motor is used for position
control in applications such as disk drives, dot matrix printers and
robotics.
Stepper motors commonly have a permanent magnet
rotor surrounded by a
stator.
The most common stepper motors have four stator windings that are
paired with a center-tapped common. This type of stepper motor is
commonly referred to as a four-phase or unipolar stepper motor. The
center tap allows a change of current direction in each of the two coils
when a winding is grounded, thereby resulting in a polarity change of
the stator.
The direction of the rotation is dictated by the
stator poles. The stator poles are determined by the current sent
through the wire coils. As the direction of the current is changed, the
polarity is also changed causing the reverse motion of the rotor.
It
should be noted that while a conventional motor shaft runs freely, the
stepper motor shaft moves in a fixed repeatable increment, which allows
one to move it to a precise position. Thus, the stepper motor moves one
step when the direction of current flow in the field coil(s) changes,
reversing the magnetic field of the stator poles. The difference between
unipolar and bipolar motors lies in the may that this reversal is
achieved.
Fig: Stepper motor operation
Advantages:
1. The rotation angle of the motor is proportional to the input pulse.
2. The motor has full torque at standstill (if the windings are energized)
3.
Precise positioning and repeatability of movement since good stepper
motors have an accuracy of 3 – 5% of a step and this error is non
cumulative from one step to the next.
4. Excellent response to starting/ stopping/reversing.
5.
Very reliable since there are no contact brushes in the motor.
Therefore the life of the motor is simply dependant on the life of the
bearing.
6. The motors response to digital input pulses provides open-loop control, making the motor simpler and less costly to control.
7. It is possible to achieve very low speed synchronous rotation with a load that is directly coupled to the shaft.
8. A wide range of rotational speeds can be realized as the speed is proportional to the frequency of the input pulses.
Disadvantages:
1. Resonances can occur if not properly controlled.
2. Not easy to operate at extremely high speeds.
Open Loop Operation:
One
of the most significant advantages of a stepper motor is its ability to
be accurately controlled in an open loop system. Open loop control
means no feedback information about position is needed. This type of
control eliminates the need for expensive sensing and feedback devices
such as optical encoders.
Stepper Motor Types:
There are three basic stepper motor types. They are :
• Variable-reluctance
• Permanent-magnet
• Hybrid
Variable-reluctance (VR)
This
type of stepper motor has been around for a long time. It is probably
the easiest to understand from a structural point of view. This type of
motor consists of a soft iron multi-toothed rotor and a wound stator.
When the stator windings are energized with DC current, the poles become
magnetized. Rotation occurs when the rotor teeth are attracted to the
energized stator poles.
Fig 1: Cross-section of a variable reluctance (VR) motor.
Permanent Magnet (PM)
The
permanent magnet step motor is a low cost and low resolution type motor
with typical step angles of 7.5° to 15°. (48 – 24 steps/revolution) PM
motors as the name implies have permanent magnets added to the motor
structure. In this type of motor, the rotor does not have teeth .
Instead the rotor is magnetized with alternating north and south poles
situated in a straight line parallel to the rotor shaft. These
magnetized rotor poles provide an increased magnetic flux intensity and
because of this the PM motor exhibits improved torque characteristics
when compared with the VR type.
PM stepper motor principle Cross section of a hybrid stepper motor
Hybrid (HB)
The
hybrid stepper motor is more expensive than the PM stepper motor but
provides better performance with respect to step resolution, torque and
speed. Typical step angles for the HB stepper motor range from 3.6° to
0.9° (100 – 400 steps per revolution).
The hybrid stepper motor
combines the best features of both the PM and VR type stepper motors.
The rotor is multi-toothed like the VR motor and contains an axially
magnetized concentric magnet around its shaft. The teeth on the rotor
provide an even better path which helps guide the magnetic flux to
preferred locations in the air gap. This further increases the detent,
holding and dynamic torque characteristics of the motor when compared
with both the VR and PM types. This motor type has some advantages such
as very low inertia and a optimized magnetic flow path with no coupling
between the two stator windings. These qualities are essential in some
applications.
When to Use a Stepper Motor:
A stepper
motor can be a good choice whenever controlled movement is required.
They can be used to advantage in applications where you need to control
rotation angle, speed, position and synchronism. Because of the inherent
advantages listed previously, stepper motors have found their place in
many different applications.
The Rotating Magnetic Field:
When
a phase winding of a stepper motor is energized with current a magnetic
flux is developed in the stator. The direction of this flux is
determined by the “Right Hand Rule” which states:
“If the coil
is grasped in the right hand with the fingers pointing in the direction
of the current in the winding (the thumb is extended at a 90° angle to
the fingers), then the thumb will point in the direction of the magnetic
field.”
The below figure shows the magnetic flux path developed
when phase B is energized with winding current in the direction shown.
The rotor then aligns itself so that the flux opposition is minimized.
In this case the motor would rotate clockwise so that its south pole
aligns with the north pole of the stator B at position 2 and its north
pole aligns with the south pole of stator B at position 6. To get the
motor to rotate we can now see that we must provide a sequence of
energizing the stator windings in such a fashion that provides a
rotating magnetic flux field which the rotor follows due to magnetic
attraction.
Fig: Magnetic flux path through a two-pole stepper motor with a lag between the rotor and stator.
Torque Generation:
The torque produced by a stepper motor depends on several factors.
• The step rate
• The drive current in the windings
• The drive design or type
In
a stepper motor, a torque will be developed when the magnetic fluxes of
the rotor and stator are displaced from each other. The stator is made
up of a high permeability magnetic material. The presence of this high
permeability material causes the magnetic flux to be confined for the
most part to the paths defined by the stator structure. This serves to
concentrate the flux at the stator poles. The torque output produced by
the motor is proportional to the intensity of the magnetic flux
generated when the winding is energized.
The basic relationship which defines the intensity of the magnetic flux is defined by:
H = (N * i) / l
where
N = The number of winding turns
i = current
H = Magnetic field intensity
l = Magnetic flux path length
This
relationship shows that the magnetic flux intensity and consequently
the torque is proportional to the number of winding turns and the
current and inversely proportional to the length of the magnetic flux
path. Thus from this basic relationship it is concluded that the same
frame size stepper motor could have very different torque output
capabilities simply by changing the winding parameters.
Step Angle Accuracy:
The
main reason that the stepper motor gained such popularity as a
positioning device is for its accuracy and repeatability. Typically
stepper motors will have a step angle accuracy of 3 – 5% of one step.
This error is also non cumulative from step to step. The accuracy of the
stepper motor is mainly a function of the mechanical precision of its
parts and assembly. Fig: Positional accuracy of a stepper motor
Torque versus Speed Characteristics:
The
torque versus speed characteristics are the key to selecting the right
motor and drive method for a specific application. These characteristics
are dependent upon (change with)the motor, excitation mode and type of
driver or drive method.
Fig: Torque versus speed characteristics
Single Step Response and Resonances:
Stepper
motors can often exhibit a phenomena referred to as resonance at
certain step rates. This can be seen as a sudden loss or drop in torque
at certain speeds which can result in missed steps or loss of
synchronism. It occurs when the input step pulse rate coincides with the
natural oscillation frequency of the rotor. Often there is a resonance
area around the 100 – 200 pps region and also one in the high step pulse
rate region. The resonance phenomena of a stepper motor comes from its
basic construction and therefore it is not possible to eliminate it
completely. It is also dependent upon the load conditions. It can be
reduced by driving the motor in half or micro stepping modes.
Fig: Single step response versus time
Few Definitions related to stepper motor:
1. Step angle
Step
angle is associated with the internal construction of the motor, in
particular the number of teeth on the stator and the rotor.
The step angle is the minimum degree of rotation associated with a single step.
Step angle
| Steps per Revolution
|
0.72
| 500
|
1.8
| 200
|
2.0
| 180
|
2.5
| 144
|
5.0
| 72
|
7.5
| 48
|
15
| 24
|
Fig: Stepper motor step angles
2. Steps per second and rpm relation
The relation between rpm (revolutions per minute), steps per revolution and steps per second is as follows:
Steps per second = (rpm*steps per revolution)/60
3. Motor speed:
The motor speed, measured in steps per second (steps/sec) is a function of the switching rate.
4. Holding torque:
The
amount of torque, from an external source, required to break away the
shaft from its holding position with the motor shaft standstill or zero
rpm condition.
STEPPER MOTOR INTERFACING WITH THE MICROCONTROLLER:
LIQUID CRYSTAL DISPLAY:
LCD stands for
Liquid
Crystal
Display.
LCD is finding wide spread use replacing LEDs (seven segment LEDs or
other multi segment LEDs) because of the following reasons:
1. The declining prices of LCDs.
2.
The ability to display numbers, characters and graphics. This is in
contrast to LEDs, which are limited to numbers and a few characters.
3.
Incorporation of a refreshing controller into the LCD, thereby
relieving the CPU of the task of refreshing the LCD. In contrast, the
LED must be refreshed by the CPU to keep displaying the data.
4. Ease of programming for characters and graphics.
These
components are “specialized” for being used with the microcontrollers,
which means that they cannot be activated by standard IC circuits. They
are used for writing different messages on a miniature LCD.
A
model described here is for its low price and great possibilities most
frequently used in practice. It is based on the HD44780 microcontroller (
Hitachi)
and can display messages in two lines with 16 characters each . It
displays all the alphabets, Greek letters, punctuation marks,
mathematical symbols etc. In addition, it is possible to display symbols
that user makes up on its own. Automatic shifting message on display
(shift left and right), appearance of the pointer, backlight etc. are
considered as useful characteristics.
Pins Functions
There
are pins along one side of the small printed board used for connection
to the microcontroller. There are total of 14 pins marked with numbers
(16 in case the background light is built in). Their function is
described in the table below:
Function
| Pin Number
| Name
| Logic State
| Description
|
Ground
| 1
| Vss
| -
| 0V
|
Power supply
| 2
| Vdd
| -
| +5V
|
Co
ntrast
| 3
| Vee
| -
| 0 - Vdd
|
Control of operating
| 4
| RS
| 0
1
| D0 – D7 are interpreted as commands
D0 – D7 are interpreted as data
|
5
| R/W
| 0
1
| Write data (from controller to LCD)
Read data (from LCD to controller)
|
6
| E
| 0
1
From 1 to 0
| Access to LCD disabled
Normal operating
Data/commands are transferred to LCD
|
Data / commands
| 7
| D0
| 0/1
| Bit 0 LSB
|
8
| D1
| 0/1
| Bit 1
|
9
| D2
| 0/1
| Bit 2
|
10
| D3
| 0/1
| Bit 3
|
11
| D4
| 0/1
| Bit 4
|
12
| D5
| 0/1
| Bit 5
|
13
| D6
| 0/1
| Bit 6
|
14
| D7
| 0/1
| Bit 7 MSB
|
LCD screen:
LCD
screen consists of two lines with 16 characters each. Each character
consists of 5x7 dot matrix. Contrast on display depends on the power
supply voltage and whether messages are displayed in one or two lines.
For that reason, variable voltage 0-Vdd is applied on pin marked as Vee.
Trimmer potentiometer is usually used for that purpose. Some versions
of displays have built in backlight (blue or green diodes). When used
during operating, a resistor for current limitation should be used (like
with any LE diode).
LCD Basic Commands
All
data transferred to LCD through outputs D0-D7 will be interpreted as
commands or as data, which depends on logic state on pin RS:
RS =
1 - Bits D0 - D7 are addresses of characters that should be displayed.
Built in processor addresses built in “map of characters” and displays
corresponding symbols. Displaying position is determined by DDRAM
address. This address is either previously defined or the address of
previously transferred character is automatically incremented.
RS
= 0 - Bits D0 - D7 are commands which determine display mode. List of
commands which LCD recognizes are given in the table below:
Command
| RS
| RW
| D7
| D6
| D5
| D4
| D3
| D2
| D1
| D0
| Execution Time
|
Clear display
| 0
| 0
| 0
| 0
| 0
| 0
| 0
| 0
| 0
| 1
| 1.64mS
|
Cursor home
| 0
| 0
| 0
| 0
| 0
| 0
| 0
| 0
| 1
| x
| 1.64mS
|
Entry mode set
| 0
| 0
| 0
| 0
| 0
| 0
| 0
| 1
| I/D
| S
| 40uS
|
Display on/off control
| 0
| 0
| 0
| 0
| 0
| 0
| 1
| D
| U
| B
| 40uS
|
Cursor/Display Shift
| 0
| 0
| 0
| 0
| 0
| 1
| D/C
| R/L
| x
| x
| 40uS
|
Function set
| 0
| 0
| 0
| 0
| 1
| DL
| N
| F
| x
| x
| 40uS
|
Set CGRAM address
| 0
| 0
| 0
| 1
| CGRAM address
| 40uS
|
Set DDRAM address
| 0
| 0
| 1
| DDRAM address
| 40uS
|
Read “BUSY” flag (BF)
| 0
| 1
| BF
| DDRAM address
| -
|
Write to CGRAM or DDRAM
| 1
| 0
| D7
| D6
| D5
| D4
| D3
| D2
| D1
| D0
| 40uS
|
Read from CGRAM or DDRAM
| 1
| 1
| D7
| D6
| D5
| D4
| D3
| D2
| D1
| D0
| 40uS
|
I/D 1 = Increment (by 1) R/L 1 = Shift right
0 = Decrement (by 1) 0 = Shift left
S 1 = Display shift on DL 1 = 8-bit interface
0 = Display shift off 0 = 4-bit interface
D 1 = Display on N 1 = Display in two lines
0 = Display off 0 = Display in one line
U 1 = Cursor on F 1 = Character format 5x10 dots
0 = Cursor off 0 = Character format 5x7 dots
B 1 = Cursor blink on D/C 1 = Display shift
0 = Cursor blink off 0 = Cursor shift
LCD Initialization :
Once
the power supply is turned on, LCD is automatically cleared. This
process lasts for approximately 15mS. After that, display is ready to
operate. The mode of operating is set by default. This means that:
1. Display is cleared
2. Mode
DL = 1 Communication through 8-bit interface
N = 0 Messages are displayed in one line
F = 0 Character font 5 x 8 dots
3. Display/Cursor on/off
D = 0 Display off
U = 0 Cursor off
B = 0 Cursor blink off
4. Character entry
ID = 1 Addresses on display are automatically incremented by 1.
S = 0 Display shift off
Automatic
reset is mainly performed without any problems. Mainly but not always!
If for any reason power supply voltage does not reach full value in the
course of 10mS, display will start perform completely unpredictably. If
voltage supply unit can not meet this condition or if it is needed to
provide completely safe operating, the process of initialization by
which a new reset enabling display to operate normally must be applied.
Algorithm
according to the initialization is being performed depends on whether
connection to the microcontroller is through 4- or 8-bit interface. All
left over to be done after that is to give basic commands and of course-
to display messages.
Fig: Procedure on 8-bit initialization.
LCD INTERFACING WITH THE MICROCONTROLLER:
![clip_image086[1]](//lh3.ggpht.com/_H-OQr197CAc/Srb9dW0DArI/AAAAAAAAATg/eIX9nh6w1uk/clip_image086%5B1%5D_thumb.gif?imgmax=800 "clip_image086[1]")
4 (RS) 1
5 (R/W) 2
6(EN) 3
LCD
D0
D1
D2
D3
D4
D5 15
D6 16
D7
|
|
P2.0
P2.1
P2.2
89C51 P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
|
|
SOFTWARES USED:
KEIL COMPILER:
Keil
compiler is a software used where the machine language code is written
and compiled. After compilation, the machine source code is converted
into hex code which is to be dumped into the microcontroller for further
processing. Keil compiler also supports C language code.
PROLOAD:
Proload
is a software which accepts only hex files. Once the machine code is
converted into hex code, that hex code has to be dumped into the
microcontroller and this is done by the Proload. Proload is a programmer
which itself contains a microcontroller in it other than the one which
is to be programmed. This microcontroller has a program in it written in
such a way that it accepts the hex file from the keil compiler and
dumps this hex file into the microcontroller which is to be programmed.
As the proload programmer kit requires power supply to be operated, this
power supply is given from the power supply circuit designed above. It
should be noted that this programmer kit contains a power supply section
in the board itself but in order to switch on that power supply, a
source is required. Thus this is accomplished from the power supply
board with an output of 12volts.
WORKING PROCEDURE:
The
Project Embedded Password based Electrical Appliances control system
using 89C51 Microcontroller is an exclusive project that provides
security at ATM centers, offices and homes.
Security is of
primary concern and in this busy, competitive world, human cannot find
ways to provide security to his confidential belongings manually.
Instead, he finds an alternative which can provide a full fledged
security as well as automized. This project has been developed on this
motto.
In this project every user, a part of an
organization, is given an unique user ID and password. The passwords of
all the users of that particular organization will be stored in EEPROM
present in the system board because the data in EEPROM can be changed
any number of times without the physical removal of the memory chip from
its socket.
This system will be fixed at the main door of the
restricted area. Whenever the user tries to enter into the organization,
this system asks the user to enter his user id. This message “Enter
USER ID” will be displayed on the LCD. Then the user has to enter his
identification number which can range from 3 to 8 numbers. The
microcontroller accepts this data and compares this user id which is
already stores in the EEPROM. If the user id is not matched with any of
the stored user ids, the microcontroller will not proceed for further
details but displays a message “Invalid USER ID”. If this user id is
matched with any one of the already stored user ids, then the system
asks the user to enter his password. After he enters his password, the
microcontroller once again compares the entered password with the
already passwords in the EEPROM. If this password matches with any one
of the passwords stored, the microcontroller opens the door by rotating
the stepper motor through ULN Driver for the person to enter into the
restricted area and the message “ Door is opening” will be displayed on
the LCD display.
But if the entered password does not match with
the already stored passwords, the message” Password failed. Enter ID”
will be displayed on the LCD and the stepper motor does not rotate.
If
the password is entered wrongly for 3 times continuously, then the
total system will be blocked. The system can come to normal condition
only after pressing the RESET switch. Initially the system is given with
default passwords as shown below.
User ID
| Password
|
101
| 100
|
102
| 200
|
103
| 300
|
104
| 400
|
The
default passwords can be changed at any time. For that “111” should be
entered when the system asks for password. After entering this code
“111: it displays “changing password” and asks “Type CURRENT PSWD”.
After entering current password, It asks for new password. The password
should not match with change password code i.e. “111”.
If the
user forgot his password then he should consult ‘administrator’. Then
the administrator enters a “10” digit code which is admin PSWD. Then the
forgotten password is displayed on LCD. Default password for
administrator is “1234567890”. ‘#’ key should be entered after
completion of entering ID or password. This key acts like a “ENTER” key.
Fig: Schematic diagram
SOURCE CODE:
WTCMD EQU 10100000B ;EEPROM 24C04 WRITE COMMAND
RDCMD EQU 10100001B ;EEPROM24C04 READ COMMAND
SCL EQU P3.6 ;SERIAL CLOCK PIN
SDA EQU P3.7 ;SERIAL DATA PIN
FAILCOUNT DATA 22H
KEYCOUNT DATA 25H ;TO STORE THE NO. KEYS ENTERD FOR EACH TIME
TEMP DATA 26H ;TEMP VARIABLE
PWDFIND DATA 27H ;TO FIND WHICH PASSWORD SHOULD BE COMPARED
PCOUNT1 DATA 28H ;TO STORE THE NO.OF DIGITS OF PASSWORD1
PCOUNT2 DATA 29H ;TO STORE THE NO.OF DIGITS OF PASSWORD2
PCOUNT3 DATA 2AH ;TO STORE THE NO.OF DIGITS OF PASSWORD3
PCOUNT4 DATA 2BH ;TO STORE THE NO.OF DIGITS OF PASSWORD4
ORG 00H
MOV P3,#00000111B ;MAKE P3.0-P3.2 AS INPUT PINS FOR COLUMNS
MOV R1,#50H ;SCANNED KEY IS STORED IN THIS LOCATION
;MOV R0,#0
CLR P2.7 ; BUZZOR OFF
MOV FAILCOUNT,#0
;LCD INTIALIZATION
MOV DPTR,#COMM
XX: CLR A
MOVC A,@A+DPTR
JZ START1
ACALL COMMAND
ACALL DELAY
INC DPTR
SJMP XX
START1:
MOV DPTR,#MSGA ;DISPLAY "WINKIT"
ACALL DISPLAY1
ACALL DELAY
MOV A,#0C0H
ACALL COMMAND
ACALL DELAY
MOV DPTR,#MSGB ;DISPLAY "LEARNING IS FUN"
ACALL DISPLAY1
ACALL DELAY
MOV DPTR,#MSG ;DISPLAY "SECURITY SYSTEM"
ACALL DISPLAY
ACALL DELAY
MOV R3,#00 ;TO CHECK ANYTHING WRITTEN IN EEPROM OR NOT
ACALL READ_FROM ;IF ANYTHING WRIITEN THEN NO NEED TO WRITE IT AGAIN GO FOR ATART
CJNE A,#0FFH,TO_START2
MOV R3,#00 ; STORE ID'S IN EEPROM ADDRESS 00H T0 0BH
MOV DPTR,#ID1 ;ID1
B1: CLR A
MOVC A,@A+DPTR
JZ F1
ACALL WRITE_TO
INC DPTR
SJMP B1
TO_START2: LJMP START2
F1: MOV R3,#03H
MOV DPTR,#ID2 ;ID2
B2: CLR A
MOVC A,@A+DPTR
JZ F2
ACALL WRITE_TO
INC DPTR
SJMP B2
F2: MOV R3,#06H
MOV DPTR,#ID3 ;ID3
B3: CLR A
MOVC A,@A+DPTR
JZ FL
ACALL WRITE_TO
INC DPTR
SJMP B3
FL: MOV R3,#09H
MOV DPTR,#ID4 ;ID4
BB: CLR A
MOVC A,@A+DPTR
JZ F3
ACALL WRITE_TO
INC DPTR
SJMP BB
/*STORE DEFAULT PASSWORDS IN EEPROM LOCATIONS 10H TO 50H */
F3: MOV R3,#10H
MOV DPTR,#PWD1 ;PASSWORD1
B4: CLR A
MOVC A,@A+DPTR
JZ F4
ACALL WRITE_TO
INC DPTR
SJMP B4
F4: MOV R3,#20H ;PASSWORD2
MOV DPTR,#PWD2
B5: CLR A
MOVC A,@A+DPTR
JZ F5
ACALL WRITE_TO
INC DPTR
SJMP B5
F5: MOV R3,#30H ;PASSWORD3
MOV DPTR,#PWD3
B6: CLR A
MOVC A,@A+DPTR
JZ F6
ACALL WRITE_TO
INC DPTR
SJMP B6
;PASSWORD4
F6: MOV R3,#40H
MOV DPTR,#PWD4
B7: CLR A
MOVC A,@A+DPTR
JZ F7
ACALL WRITE_TO
INC DPTR
SJMP B7
F7: MOV R3,#50H
MOV DPTR,#ADMINPWD ;ADMIN PASSWORD
B8: CLR A
MOVC A,@A+DPTR
JZ STRT
ACALL WRITE_TO
INC DPTR
SJMP B8
/*STORE THE NO.OF DIGITS OF PASSWORDS AS 3 INTIALLY*/
STRT: MOV R3,#19H
MOV A,#3
ACALL WRITE_TO
MOV R3,#29H
MOV A,#3
ACALL WRITE_TO
MOV R3,#39H
MOV A,#3
ACALL WRITE_TO
MOV R3,#49H
MOV A,#3
ACALL WRITE_TO
START2:
CLR P2.7
MOV DPTR,#MSG1 ;ASKING FOR ID
ACALL DISPLAY
ACALL DELAY
ACALL KEYSCAN ;ENTER THE ID
ACALL DELAY
ACALL COMPARISON ;ID COMPARISION
ACALL DELAY
SJMP START2
WRITE_TO:
MOV R4,A ;DATA IS STORED IN R4
ACALL WRITE ;WRITE THE DATA INTO EEPROM
INC R3
;ACALL DELAY
RET
READ_FROM:
ACALL READ ;READ THE DATA FROM 24C04 FROM THE MEMORY
ACALL DELAY
INC R3
RET
WRITE:
MOV A,#WTCMD ;DEV ADDRS IN WRITE MODE
ACALL OUTS
MOV A,R3 ;DATA ADDRS
ACALL OUT
MOV A,R4 ;DATA
ACALL OUT
ACALL STOP ;STOP
RET
READ:
MOV A,#WTCMD
ACALL OUTS
MOV A,R3
ACALL OUT
MOV A,#RDCMD
ACALL OUTS
ACALL IN
ACALL STOP
RET
OUTS:
MOV B,#8
SETB SDA ; BUS FREE AND START CONDITION
SETB SCL
NOP
CLR SDA
NOP
CLR SCL
OSLOOP:
RLC A
MOV SDA,C
SETB SCL
NOP
CLR SCL
DJNZ B,OSLOOP
SETB SDA
NOP
SETB SCL
NOP
CLR SCL
RET
OUT:
MOV B,#8
OLOOP:
RLC A
MOV SDA,C
SETB SCL
NOP
CLR SCL
DJNZ B,OLOOP
SETB SDA
NOP
SETB SCL
NOP
CLR SCL
RET
IN:
MOV B,#8
SETB SDA
INLOOP:
CLR SCL
NOP
SETB SCL
MOV C,SDA
RLC A
DJNZ B,INLOOP
CLR SCL
RET
STOP: ;I2C STOP CONDITION
CLR SDA
NOP
SETB SCL
NOP
SETB SDA
LCALL DLAYms
RET
/*@@@@@@@ KEYSCAN SUBROUTINE @@@@@@@@@@@@@@@*/
KEYSCAN: MOV R1,#50H ;SCANNED KEY IS STORED IN THIS LOCATION
MOV A,#0C3H ;ENTERD KEYS ARE DISPLAYED FROM 4TH LOCATION OF 2ND LINE
LCALL COMMAND
LCALL DELAY
MOV KEYCOUNT,#0
NEXTKEY: MOV P0,#0F0H ;GROUND ALL ROWS INTIALLY
MOV A,P3 ;READ ALL COLMNS;ENSURE ALL KEYS OPEN
ANL A, #00000111B
CJNE A,#00000111B,NEXTKEY
K2: ACALL DELAY
MOV A,P3 ;READ ALL COLMNS;ENSURE ALL KEYS OPEN
ANL A, #00000111B
CJNE A,#00000111B,OVER
SJMP K2
OVER: ACALL DELAY
MOV A,P3 ;READ ALL COLMNS
ANL A, #00000111B
CJNE A,#00000111B,OVER1
SJMP K2
OVER1: MOV P0,#00001110B ;GROUND ROW 0
MOV A,P3 ;READ ALL COLMNS
ANL A, #00000111B
CJNE A,#00000111B,ROW_0
MOV P0,#00001101B ;GROUND ROW 1
MOV A,P3 ;READ ALL COLMNS
ANL A, #00000111B
CJNE A,#00000111B,ROW_1
MOV P0,#00001011B ;GROUND ROW 2
MOV A,P3 ;READ ALL COLMNS
ANL A, #00000111B
CJNE A,#00000111B,ROW_2
MOV P0,#00000111B ;GROUND ROW 3
MOV A,P3 ;READ ALL COLMNS
ANL A, #00000111B
CJNE A,#00000111B,ROW_3
LJMP K2
ROW_0: MOV DPTR,#KCODE0
SJMP FIND
ROW_1: MOV DPTR,#KCODE1
SJMP FIND
ROW_2: MOV DPTR,#KCODE2
SJMP FIND
ROW_3: MOV DPTR,#KCODE3
FIND: RRC A
JNC MATCH
INC DPTR
SJMP FIND
MATCH:
SETB P2.7
ACALL DELAY ;IF KEY IS DETECTED THEN GIVE A BEEP SOUND
ACALL DELAY
CLR P2.7
CLR A
MOVC A,@A+DPTR
MOV @R1,A
CJNE A,#23H,NK ;STOP THE KEYSCANNING WHEN '#' IS PRESSED
RET
NK: ACALL DATAWRT ;DISPLAY THE PRESSED KEY
ACALL DELAY
INC KEYCOUNT
INC R1
SJMP NEXTKEY
COMPARISON:
MOV A,KEYCOUNT
CJNE A,#3,FFAIL
MOV R3,#00H ;EEPROM LOCATION
CHECKID1: LCALL READ_FROM ;COMPARE WITH ID1
CJNE A,50H,CHECKID2
LCALL READ_FROM
CJNE A,51H,CHECKID2
LCALL READ_FROM
CJNE A,52H,CHECKID2
SJMP PWDCHECK1 ;IF ID MATCHED GO FOR ITS PASSWORD
;COMPARE WITH ID2
CHECKID2: MOV R3,#03H
LCALL READ_FROM
CJNE A,50H,CHECKID3
LCALL READ_FROM
CJNE A,51H,CHECKID3
LCALL READ_FROM
CJNE A,52H,CHECKID3
SJMP PWDCHECK2
;COMPARE WITH ID3
CHECKID3: MOV R3,#06H
LCALL READ_FROM
CJNE A,50H,CHECKID4
LCALL READ_FROM
CJNE A,51H,CHECKID4
LCALL READ_FROM
CJNE A,52H,CHECKID4
SJMP PWDCHECK3
;COMPARE WITH ID4
CHECKID4: MOV R3,#09H
LCALL READ_FROM
CJNE A,50H,FFAIL
LCALL READ_FROM
CJNE A,51H,FFAIL
LCALL READ_FROM
CJNE A,52H,FFAIL
LJMP PWDCHECK4
FFAIL: LJMP FAIL
PWDCHECK1: MOV PWDFIND,#10000001B ;TO SET 8th,1st BIT THIS LOGIC IS USED TO KNOW WHICH ID'S PASSWORD SHOULD BE COMPARED
MOV DPTR,#MSG2 ;ASK FOR PASSWORD
ACALL DISPLAY
ACALL KEYSCAN ;ENTER PASSWORD
ACALL DELAY
MOV A,KEYCOUNT
CJNE A,#10,PD1 ;IF NO.OF KEYS ENTERD ARE 10 THEN GO COMPARE WITH ADMINPASSWORD
LJMP ADMIN_PSWD
PD1: MOV R3,#19H
LCALL READ_FROM
MOV PCOUNT1,A ;LOAD THE NO.OF DIGITS OF PASSWORD1 IN PCOUNT1
MOV R3,#10H
MOV R2,#10H
ACALL PWDCHANGE ;CHECK WHETHER USER WANTS TO CHANGE PASSWORD OR NOT
MOV R3,#19H ;IF PASSWORD IS CHANGED THEN STORE THE NO.OF DIGITS OF NEW PASSWORD
MOV A,TEMP
LCALL WRITE_TO
LJMP START2
PWDCHECK2: MOV PWDFIND,#01000010B ;TO SET 7th AND 2nd BIT
MOV DPTR,#MSG2
ACALL DISPLAY
ACALL KEYSCAN
ACALL DELAY
MOV A,KEYCOUNT
CJNE A,#10,PD11
LJMP ADMIN_PSWD
PD11:
MOV R3,#29H
LCALL READ_FROM
MOV PCOUNT2,A
MOV R3,#20H
MOV R2,#20H
ACALL PWDCHANGE
MOV R3,#29H
MOV A,TEMP
LCALL WRITE_TO
LJMP START2
PWDCHECK3: MOV PWDFIND,#00100100B ;TO SET 6th,3rd BIT
MOV DPTR,#MSG2
ACALL DISPLAY
ACALL KEYSCAN
ACALL DELAY
MOV A,KEYCOUNT
CJNE A,#10,PD111
LJMP ADMIN_PSWD
PD111: MOV R3,#39H
LCALL READ_FROM
MOV PCOUNT3,A
MOV R3,#30H
MOV R2,#30H
ACALL PWDCHANGE
MOV R3,#39H
MOV A,TEMP
LCALL WRITE_TO
LJMP START2
PWDCHECK4: MOV PWDFIND,#00011000B ;TO SET 5th,4th BIT
MOV DPTR,#MSG2
ACALL DISPLAY
ACALL KEYSCAN
ACALL DELAY
MOV A,KEYCOUNT
CJNE A,#10,PD1111
LJMP ADMIN_PSWD
PD1111: MOV R3,#49H
LCALL READ_FROM
MOV PCOUNT4,A
MOV R3,#40H
MOV R2,#40H
ACALL PWDCHANGE
MOV R3,#49H
MOV A,TEMP
LCALL WRITE_TO
LJMP START2
PWDCHANGE:
MOV A,KEYCOUNT
CJNE A,#3,INTIALCHECK ;IF NO.OF KEYS ENTERD ARE 3 THEN CHECK FOR NEWPASSWORD REQUEST
MOV A,#'1'
CJNE A,50H,INTIALCHECK
CJNE A,51H,INTIALCHECK
CJNE A,52H,INTIALCHECK
;IF IT IS NEWPASSWORD REQUEST THEN ALLOW FOR GIVE NEWPASSWORD
NEWPSWD: MOV DPTR,#MSG5
ACALL DISPLAY
ACALL DELAY
MOV DPTR,#MSG6
ACALL DISPLAY ;CHECK CURRENT PSWD
ACALL DELAY
LCALL KEYSCAN
ACALL DELAY
ACALL CHECKPWD ;IF OLD PASSWORD IS ENTERD CORRECTLY THEN GO FOR NEW PASSWORD
MOV A,R2
MOV R3,A
TRY: MOV DPTR,#MSG7
ACALL DISPLAY
ACALL DELAY
LCALL KEYSCAN ;TYPE NEW PSWD
ACALL DELAY
MOV A,#3
CJNE A,KEYCOUNT,ACCEPT
MOV A,#'1'
CJNE A,50H,ACCEPT
CJNE A,51H,ACCEPT
CJNE A,52H,ACCEPT
MOV DPTR,#MSG12
ACALL DISPLAY
ACALL DELAY
SJMP TRY
ACCEPT: MOV TEMP,KEYCOUNT
MOV A,KEYCOUNT
CJNE A,#10,LK
MOV DPTR,#MSG9
ACALL DISPLAY
SJMP TRY
LK: MOV R1,#50H ;WRITE THE NEW PASSWORD IN EEPROM
LL: MOV A,@R1
LCALL WRITE_TO
INC R1
DJNZ KEYCOUNT,LL
RET
INTIALCHECK: ACALL CHECKPWD
ACALL DELAY
LJMP SUCCESS
CHECKPWD: JB PWDFIND.7,PSWD1
JB PWDFIND.6,PSWD2
JB PWDFIND.5,PSWD3
JB PWDFIND.4,PSWD4
LJMP START2
PSWD1: MOV A,PCOUNT1
SJMP JJJ
PSWD2: MOV A,PCOUNT2
SJMP JJJ
PSWD3: MOV A,PCOUNT3
SJMP JJJ
PSWD4: MOV A,PCOUNT4
JJJ: CJNE A,KEYCOUNT,FAIL
MOV R1,#50H
JJ: LCALL READ_FROM
MOV TEMP,@R1
CJNE A,TEMP,FAIL
INC R1
DJNZ KEYCOUNT,JJ
RET
ADMIN_PSWD: MOV R1,#50H ;RAM LOCATION
MOV R3,#50H ;EEPROM LOCATION
RPT: LCALL READ_FROM
MOV TEMP,@R1
CJNE A,TEMP,FAIL
INC R1
DJNZ KEYCOUNT,RPT
;IF ADMIN PASSWORD IS MATCHED THEN DISPLAY THE RESPECTIVE USER'S PASSWOR
MOV DPTR,#MSG8
ACALL DISPLAY
JB PWDFIND.0,DISP_PWD1
JB PWDFIND.1,DISP_PWD2
JB PWDFIND.2,DISP_PWD3
JB PWDFIND.3,DISP_PWD4
DISP_PWD1: MOV R3,#10H ;DISPLAY PASSWORD1
MOV TEMP,PCOUNT1
SJMP DO_AGAIN
;DISPLAY PASSWORD2
DISP_PWD2: MOV R3,#20H
MOV TEMP,PCOUNT2
SJMP DO_AGAIN
;DISPLAY PASSWORD3
DISP_PWD3: MOV R3,#30H
MOV TEMP,PCOUNT3
SJMP DO_AGAIN
;DISPLAY PASSWORD4
DISP_PWD4: MOV R3,#40H
MOV TEMP,PCOUNT4
DO_AGAIN:
MOV A,#0C4H
ACALL COMMAND
ACALL DELAY
DO_AGAIN1: LCALL READ_FROM
ACALL DATAWRT
ACALL DELAY
DJNZ TEMP,DO_AGAIN1
ACALL DLAYms
ACALL DLAYms
ACALL DLAYms
ACALL DLAYms
LJMP START2
SUCCESS: MOV FAILCOUNT,#0
MOV DPTR,#MSG3 ;IF THE ID & PSWD ARE MATCHED THEN STEEPPER MOTOR ROTATES
ACALL DISPLAY
ACALL STEPPER
LJMP START2
;IF NOT MATCHED THEN GIVE THREE BEEP SOUNDS
FAIL:
MOV DPTR,#MSG4
ACALL DISPLAY
INC FAILCOUNT
MOV A,#3
CJNE A,FAILCOUNT,TRY1
MOV FAILCOUNT,#0
MOV DPTR,#MSG13
ACALL DISPLAY
SETB P2.7
SJMP $
TRY1: SETB P2.7
ACALL DLAYms
ACALL DLAYms
CLR P2.7
ACALL DELAY
ACALL DELAY
SETB P2.7
ACALL DLAYms
ACALL DLAYms
CLR P2.7
ACALL DELAY
ACALL DELAY
SETB P2.7
ACALL DLAYms
ACALL DLAYms
LJMP START2
STEPPER: MOV DPTR,#MSG10
ACALL DISPLAY
ACALL DELAY
MOV TEMP,#15
ROTATE_R: ;ROTATE CLOCKWISE
MOV P2,#06H
ACALL DELAY
MOV P2,#03H
ACALL DELAY
MOV P2,#09H
ACALL DELAY
MOV P2,#0CH
ACALL DELAY
DJNZ TEMP,ROTATE_R
MOV P2,#0
ACALL L_DELAY
ACALL L_DELAY
ACALL L_DELAY
MOV DPTR,#MSG11
ACALL DISPLAY
ACALL DELAY
MOV TEMP,#15
ROTATE_L: ;ROTATE ANTI CLOCKWISE
MOV P2,#06H
ACALL DELAY
MOV P2,#0CH
ACALL DELAY
MOV P2,#09H
ACALL DELAY
MOV P2,#03H
ACALL DELAY
DJNZ TEMP,ROTATE_L
RET
/* LCD DISPLAY SUBROUTINE */
DISPLAY: MOV A,#01H
ACALL COMMAND
ACALL DELAY
DISPLAY1: CLR A
MOVC A,@A+DPTR
JZ XYZ
ACALL DATAWRT
ACALL DELAY
INC DPTR
SJMP DISPLAY1
XYZ: MOV A,#0C4H
ACALL COMMAND
ACALL DELAY
RET
COMMAND: ;SEND COMMANDS TO LCD
MOV P1,A
CLR P3.3
CLR P3.4
SETB P3.5
ACALL DELAY
CLR P3.5
RET
DATAWRT: ;SEND DATA TO LCD
MOV P1,A
SETB P3.3
CLR P3.4
SETB P3.5
ACALL DELAY
CLR P3.5
RET
DELAY:
MOV R6,#200
HERE1: MOV R7,#100
HERE: DJNZ R7,HERE
DJNZ R6,HERE1
RET
DLAYms:
MOV R6,#100
MOV B,#00
MS1: DJNZ B,$
DJNZ B,$
DJNZ R6,MS1
RET
L_DELAY:
MOV R7,#0AH
LLL: LCALL DLAYms
DJNZ R7,LLL
RET
COMM: DB 38H,0EH,01H,06H,84H,00H
ID1: DB "101",0
ID2: DB "102",0
ID3: DB "103",0
ID4: DB "104",0
PWD1: DB "100",0
PWD2: DB "200",0
PWD3: DB "300",0
PWD4: DB "400",0
ADMINPWD: DB "1234567890",0
MSGA: DB "WINKIT",0
MSGB: DB "LEARNING IS FUN",0
MSG : DB "SECURITY SYSTEM",0
MSG1: DB "ENTER ID",0
MSG2: DB "ENTER PASSWORD",0
MSG3: DB "SUCCESS",0
MSG4: DB "FAIL",0
MSG5: DB "CHANGE PASSWORD",0
MSG6: DB "TYPE CURRENT PWD",0
MSG7: DB "ENTER NEW PSWD",0
MSG8: DB "YOUR PSWD IS ",0
MSG9: DB "MAX LENTH OVER ",0
MSG10: DB "DOOR IS OPENING ",0
MSG11: DB "DOOR IS CLOSING ",0
MSG12: DB "INVALID PSWD ",0
MSG13: DB " SYSTEM BLOCKED ",0
KCODE0: DB '1','2','3'
KCODE1: DB '4','5','6'
KCODE2: DB '7','8','9'
KCODE3: DB '*','0','#'
END
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